Capacitor sizing is a crucial step when designing charge-scaling digital-to-analog converters (DACs). Larger capacitor size can achieve better circuit accuracy and performance due to less impact from process gradient, parasitic mismatch, and local variation. However, it also results in larger chip area and higher power consumption. The size of binary-weighted capacitors in charge-scaling DACs is highly sensitive to the routing parasitics. Unmatched routing parasitics among binary-weighted capacitors will lead to large capacitor size for satisfying circuit accuracy and performance. Previous work focuses on the study of generating high-quality common-centroid placement of unit capacitor arrays while ignoring routing parasitics. None of them address the sizing of binary-weighed capacitors.
The charge-scaling digital-to-analog converters (DACs) is one of the most important and common implementations of the successive-approximation-register (SAR) analog-to-digital converters (ADCs) which has the advantage of lower power consumption and is widely used in many biomedical or battery-powered circuits and systems. It consists of an array of individually switched binary-weighted capacitors and a comparator, which perform a binary search in conjunction with SARs. The accuracy and performance of a charge-scaling DAC are highly correlated with the accuracy of capacitance ratio of binary-weighted capacitors, while the power consumption of a charge-scaling DAC depends on absolute capacitance values.
Although layout synthesis techniques for ratioed capacitors had been extensively studied, most of the previous works only emphasized how to generate highly matched common-centroid and/or dispersive placements for ratioed capacitors to minimize the impact from process-gradient-induced mismatch. They failed to consider the routing parasitics which may destroy the resulting matching properties of ratioed capacitors, even if the placement is perfectly matched.
When designing the capacitor layout of a charge-scaling DAC, the accuracy of capacitance ratios correlates closely with the matching properties among the binary-weighted capacitors and the induced parasitics due to interconnecting wires. Some of the parasitic capacitors may affect the stability of reference voltage. To minimize the impact on circuit accuracy due to the parasitic capacitors, a simple yet effective approach is to enlarge the capacitance of all binary-weighted capacitors. However, such an approach may not be suitable for modern battery-powered system-on-chips (SoCs) because the large capacitance values of binary-weighted capacitors will significantly increase both chip area and power consumption.
None of the previous works mentioned how to simultaneously minimize unit capacitor size and match routing parasitics during common-centroid layout generation of unit capacitor arrays. Therefore, the present invention simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied.